Bus Notation are No Joke!

Imagine the following scenario:

You’ve finally survived rigorous simulation tests, a brutal place-and-route run, and a mountain of DRCs. You finally make it to LVS, only to be greeted by a wall of errors that seem to have materialized out of thin air.

After a week of debugging; going to the desperate lengths of building a stripped-down test chip just to test your flow and sanity, you finally find the culprit: the circuit designer used mismatched bus notation orders between their lib and lef files.

To them, flipping the indexing might seem insignificant. But to an automated tool that is essentially guessing blindly to match the layout to the schematic, this is the hardware equivalent of sliding down a water slide straight into a brick wall (splat!).

This is why we stick to the standard convention: bus[MSB:LSB]. It’s intuitive (MSB is on the left, just like every normal number we write), and it keeps the verification flow from crashing.

Moral of the story: Don't mess with bus orders unless you absolutely have to; and even then, only if you truly know what you're doing.