EYAL YEMINI

[email protected] | GitHub | LinkedIn

PROFESSIONAL SUMMARY

Detail-oriented Electrical and Computer Engineering researcher and engineer specializing in Digital Design, VLSI, and full-flow ASIC development. Proven expertise spanning RTL architecture, mixed-signal integration, and physical design (RTL-to-GDSII). Academic track record includes serving as a VLSI Teaching Assistant and conducting advanced graduate research on Processing-in-Memory (PIM) hardware accelerators.

TECHNICAL SKILLS

• Languages: Python, C, C++, Verilog, SystemVerilog, Assembly (8086), TCL
• Tools & Frameworks: Linux, Git, Cadence Virtuoso, LaTeX, Genus, Voltus, Innovus, Xcelium

EDUCATION

• M.Sc. in Electrical Engineering | Bar-Ilan University (2025 – Present)

• Research Focus: Memristor-based memory architectures and Processing-in-Memory (PIM) hardware accelerators.

• B.Sc. in Computer Engineering (Hardware & Chip Design Track) | Bar-Ilan University (2021 – 2025)

• GPA: 89

• Specialization: Digital Design, VLSI, and Hardware Development

RESEARCH and PROJECTS

Full-Flow ASIC Design Engineer – PIM Accelerator

• Delivered a complete 1T1R-NOR memristor array for Processing-in-Memory from initial physical design to final GDSII generation.
• Architected critical support structures, integrating custom power delivery and advanced sensing circuitry with digital controller RTL.
• Created behavioral models to anchor the verification strategy and guarantee system functionality.
• Managed the physical backend implementation, including place-and-route (PnR) setup, static timing analysis (STA), and strict DRC/LVS sign-off compliance.

SoftMax Accelerator (ASIC) – Enics Labs' XBOX SoC Platform

• Developed SystemVerilog RTL modules, including finite state machines (FSMs), multiplexers, and pipelined datapaths.
• Integrated hardware into the platform and wrote embedded test software.
• Built testbenches and coverage scripts to validate architectural feasibility.

Assembly and Microcontrollers

• Wrote drivers and applications for 8086 simulators, ADuC841, ESP32, and Arduino.

PROFESSIONAL EXPERIENCE

• Teaching Assistant – DDP and VLSI Courses | Bar-Ilan University (2025 – Present)
• Deliver hands-on lab sessions covering RTL simulation, logic synthesis, and the complete backend implementation flow (RTL-to-GDSII).
• Author comprehensive coursework assignments and construct automated SystemVerilog verification testbenches for student evaluation.
• Provide technical guidance on Linux environments, tool automation, and Cadence Xcelium workflows.

MILITARY SERVICE

• Radio Technician Team Lead – Oz "89" Brigade (2015 – 2018)
• Supervised a team of 6–8 technicians responsible for radio systems maintenance and inspection.
• Handled complex technical troubleshooting, team training, and documentation workflows.